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TIMING CHARACTERISTICS 1, 2 0.5%
ADE7757
(V DD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, RCLKIN = 6.2 k ? ,
50 ppm/ C, T MIN to T MAX = –40 C to +85 C, unless otherwise noted.)
Parameter
A, B Versions
Unit
Test Conditions/Comments
t 1
3
244
ms
F1 and F2 Pulse Width (Logic Low).
t 2
t 3
t 43, 4
t 5
t 6
See Table II
1/2 t 2
173
See Table III
2
sec
sec
ms
sec
μ s
Output Pulse Period. See Transfer Function section.
Time between F1 Falling Edge and F2 Falling Edge.
CF Pulse Width (Logic High).
CF Pulse Period. See Transfer Function section.
Minimum Time between F1 and F2 Pulses.
NOTES
1
2
3
4
Sample tested during initial release and after any redesign or process change that may affect this parameter.
See Figure 1.
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section.
The CF pulse is always 35 μ s in the high frequency mode. See Frequency Outputs section and Table III.
Specifications subject to change without notice.
t 1
F1
t 6
t 2
F2
t 4
t 3
t 5
CF
Figure 1. Timing Diagram for Frequency Outputs
REV. A
–3 –
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